// *******************************************************************************************************
//! LIST | CONTEXT | NOTE
//! ---  | ---     | --- 
//! Company | Fpga Publish
//! Engineer| worker fu   
//! 
//! Create Date | 2024/11/02 23:24:50
//! Design Name | PL
//! Module Name | view_eyes_core_plat
//! Project Name| VIEW_EYES 
//! Target Devices| ZYNQ7010 & XCZU2CG & Kintex7 & A10
//! Tool Versions | vivado2021.1 & quartus2018
//! Description   | what it design?
//!         1     | 
//! Dependencies  | how it work?
//!         1     | 
//! Revision      | when it update?
//!          0.01 | File Created
//! Additional Comments | where it supoort?
//!          Xilinx     | https://www.xilinx-china.cn/
// *******************************************************************************************************
// ###################################################################################
// file include and scale define
`timescale 1ns / 1ps
module view_eyes_core_plat #(
    //monitor interface
    parameter WD_LINE_LED   = 8,
    // -----------------------
    parameter MD_SIM_ABLE = 0, //! mode  of sim enable
    parameter WD_ERR_CODE = 4  //! width of err info 
   )(
    //led monitor
    output  [WD_LINE_LED-1:0]    o_port_led_line, //! led light port

    //! system signals
    input           i_port_sys_clk   //! clock 
);



// =========================================================================
// function and localparam to converation and calculate

// =========================================================================
// register and wire to time sequence and combine
// ----------------------------------------------------------
// clock var
wire w_bufg_sys_clk;
wire w_pll_rst   ; //! pll reset
reg [7:0] r_pll_rst_cnt = 0;
wire w_sys_clk   ; //! system run clock
wire w_sys_resetn; //! system resetn by PLL


// ----------------------------------------------------------
// led var
wire [WD_LINE_LED-1:0] w_trig_led_light; //! led light control
assign w_trig_led_light = {WD_LINE_LED{1'b1}}; //all led work default

// =========================================================================
// module / task / always / assign to drive logic and connect
// ---------------------------------------------------------------
// clock generate subsystem

always@(posedge w_bufg_sys_clk)
begin:LOGIC_R_PLL_RST_CNT
    if(1) //update in one cycle
    begin
        r_pll_rst_cnt <= r_pll_rst_cnt[7] ? r_pll_rst_cnt :
                         r_pll_rst_cnt + 1'b1;
    end
end
assign w_pll_rst = ~r_pll_rst_cnt[7]; // reset when start
altclkctrl u_altclkctrl(
    .inclk ( i_port_sys_clk ),
    .outclk  ( w_bufg_sys_clk  )
);

pll u_pll(
    .rst       ( w_pll_rst       ),
    .refclk    ( w_bufg_sys_clk  ),
    .locked    ( w_sys_resetn    ),
    .outclk_0  ( w_sys_clk       )
);


// ---------------------------------------------------------------
// monitor subsystem
led_line_driv#(
    .WD_LED           ( WD_LINE_LED ),
    .WD_DELAY_CNT     ( 27 ),
    .MD_DEFAULT_INV   ( 0 ),
    .MD_SIM_ABLE      ( 0 ),
    .WD_ERR_INFO      ( 4 )
)u_led_line_driv(
    .i_sys_clk        ( w_sys_clk        ),
    .i_sys_resetn     ( w_sys_resetn     ),
    .i_trig_led_light ( w_trig_led_light ),
    .o_port_led_line  ( o_port_led_line  ),
    .m_err_led_info1  (   )
);

// =========================================================================
// ila and vio and error code to debug and monitor



endmodule
// ###################################################################################
// foot note of it
// please follow MIT when you want to ust it 